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资源信息:
中文名: 数字信号开发
英文名: Altera Quartus II DSP Builder
资源格式: 光盘镜像
版本: V9.1 incl SP2 Linux
发行时间: 2010年
制作发行: Altera Corporation
地区: 美国
语言: 英文
概述:
官方站点 http://www.altera.com/products/software/qu...dex.html
利用DSP Builder技术,您在几分钟内就可以使用业界标准The MathWorks/Simulink工具完成系统定义/仿真,直至系统实现。
DSP Builder信号编译器模块读取由DSP Builder和MegaCore®模块构建的Simulink模型文件(.mdl),生成VHDL文件和工具命令语言(Tcl)脚本,进行综合,实现硬件,并完成仿真。
Altera与The Mathworks密切协作,确保您获得Altera® FPGA的性价比优势,同时能够使用Simulink——The MathWorks基于模型设计的业界最佳工具。
Altera的Simulink至FPGA综合技术在业界独具特色,它现在支持Simulink设计表征时序驱动综合。利用该技术,您第一次能够自动生成基于高级Simulink设计描述的时序最佳寄存器传送级(RTL)代码。使用这一新的DSP Builder功能,您在几分钟内就可以实现高性能设计,达到峰值FPGA性能。相对于手动优化HDL代码需要的数小时甚至几天时间相比,这大大提高了效能。
What's new in Quartus II design software version 9.1?
Quartus® II software version 9.1 delivers the #1 performance and productivity for FPGA, CPLD, and HardCopy® ASIC designs. This new release supports Altera's new lowest cost, lowest power FPGA family—Cyclone® IV GX FPGAs with integrated 3.125-Gbps transceivers. The Cyclone IV GX FPGA family is targeted to high-volume, cost-sensitive applications, enabling you to meet increasing bandwidth requirements while lowering costs. Version 9.1 further extends Quartus II software's productivity advantage by delivering 20 percent overall compile time reduction over Quartus II software version 9.0, and maintains 2x to 3x faster compile times than the nearest competitor for high-density 65-nm and 40-nm designs. In addition, the new Rapid Recompile feature in version 9.1 reduces compile times by 50 percent (on average) compared to a full compile when small engineering change order (ECO)-type design changes are made. Finally, this release also supports the largest FPGA in the industry—Stratix® IV E EP4SE820 devices.
New Rapid Recompile for Faster Design Iteration
The new Rapid Recompile feature enhances Quartus II software's ability to further minimize design compilation times. Rapid Recompile maximizes productivity by enabling faster small ECO-type design changes after a full compile, reducing compilation times by 50 percent (on average) versus running another full compile on the design. Rapid Recompile also significantly improves productivity during timing closure by preserving critical timing during late design changes.
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